The present invention relates, in general, to packaging techniques, and more particularly, to a novel semiconductor package.
In the past, the semiconductor industry has utilized a variety of encapsulation techniques for forming the body of semiconductor packages. Typically, the semiconductor and other devices are assembled onto an interconnect platform or substrate such as a leadframe, printed circuit board or ceramic substrate. One particular encapsulating technique, commonly referred to as glob-top, involves dispensing an encapsulant to cover semiconductor devices or other components that are assembled onto the substrate. One problem with this prior technique is the planarity of the top surface of the encapsulant. Often, the top surface has a convex shape. Because of the convex shape, automated pick and place equipment can not utilize the resulting semiconductor package. Also, it is difficult to mark the top surface because of the convex shape.
Such techniques usually encapsulate a single assembly site on a substrate and after encapsulation, the assembly site is singulated to form an individual package. Consequently, assembly time and singulation time are long and result in high package cost.
Accordingly, it is desirable to have a semiconductor package that has a substantially planar surface that can be utilized with automated pick and place equipment, that is easily marked, and that increases throughput thereby reducing the cycle time and assembly costs.